A description of SDRAMs may be found in the article "Synchronous DRAMs: Designing to the JEDEC Standard", in MICRON Design Line, volume 2, Issue 2, No 2Q93.
Synchronous DRAMs can utilize different CAS latency modes of operation. For example, for a CAS latency of 1, data which is read by its data bus read amplifier arrives at its output buffer after the clock. For a CAS latency of 3, the data waits for the clock at a stage preceding the output buffer. For a latency of 2 there is a race condition between the data and the clock to the output buffer.